In digital signal processing it is necessary to convert an analog signal into a digital format. To insure reasonable fidelity in this conversion, it is desirable to sample the analog signal at a rate substantially greater than analog signal bandwidth. These sampled signal values are then converted sample by sample at high speed into their equivalent digital values represented by N number of binary bits. Prior art ADCs, which typically use bipolar transistors, are able to operate at high rates (e.g., 50 MHz) and with 10-bit resolution. These ADCs require relatively large amounts of power and are very costly. On the other hand, attempts to implement high speed, multi-bit ADCs with MOS technology have not been as successful as desired. Either cost was high because of poor chip yield or performance was substantially less than could be obtained using bipolar transistor technology.
One of the problems in implementing a high speed ADC in MOS technology is that of noise caused by induced currents in the silicon substrate of a MOS chip. To some extent this problem can be minimized by careful shielding, by the separation and isolation of power supply busses, and by the use of complementary metal oxide semiconductor (CMOS) transistors, that is, n-channel and p-channel MOS transistors (NMOS and PMOS). However, the presence of residual noise, switching transients, stray capacity, etc., impose certain design constraints and other limitations on the sensitivity and sampling speed of an ADC using MOS technology as discussed in my U.S. Pat. No. 4,989,003.
Another problem is that the individual transistors and capacitors in a MOS circuit may have values of threshold voltage, capacitance, etc., which can vary by as much as 10%. These variations make it extremely difficult to build a high speed, precision ADC requiring closely matched components, without the use of component trimming, which is costly, and without the use of switched capacitor auto-zero input circuitry which causes large input switching transients.
An N-flash ADC, simultaneously produces N data bits in parallel from a sampled analog voltage. The ADC comprises 2.sup.N -1 comparators which are closely matched to each other with each capable of high resolution. The ADC circuit momentarily connects all of these comparators at once to an input signal circuit. This input switching is used in conventional MOS comparator circuitry which uses switched capacitor auto-zero input circuitry to compensate for relatively large MOS threshold voltage offsets. A decoder circuit coupled to all of the comparators then determines the values of the N bits corresponding to the analog value of the input signal being sampled at that instant. An advantage of this type of ADC is the high speed at which it can operate. An important disadvantage is the relatively low impedance load (and corresponding large switching transients) caused by connecting all of the comparators to the input circuit at the same time. As an example, for a 10 bit output ADC (where N equals 10) the number of comparators is 1023!Thus the applied load represented by all the comparators connected in parallel is hundreds of times greater than that of a single comparator alone, giving rise to undesirably large switching transients. An important reason for reducing the magnitude of these switching transients is that the recovery time from these transients sets the upper limit on the sampling rate of the ADC. This undesirable condition is aggravated in MOS technology where the input source impedance levels are inherently high, causing switching transients to be more pronounced than with bipolar technology.
A serial ADC, samples an analog signal and then bit-by-bit determines the digital value of the sample. A single comparator in the ADC is used to determine all of the bit values. This single comparator presents a smaller load and thus reduced switching transients compared to an N-flash ADC. The speed of a serial ADC, however, is relatively low because of the time taken in the sequential determination of the bit values of the digital output. Thus to produce a 10-bit value, a serial ADC may run at only one-tenth the speed of a 10-bit N-flash ADC. It will thus be appreciated that the requirement for high speed in an ADC may conflict in important ways with the requirement for high resolution; and that the desire for low cost, through the use of MOS technology, may conflict with the desire for high performance.
It is desirable to have a high speed and relatively low cost ADC formed on a semiconductor substrate using MOS technology which may be integrated with digital MOS circuitry on the same semiconductor substrate.